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Achieving a Half-Billion IOPs in a 1U REDIS server with FPGA Acceleration
Speaker(s): John Lockwood
Field Programmable Gate Arrays (FPGAs) are drastically increasing the speed of database servers. By implementing a Key-Value Store (KVS) entirely in FPGA logic, servers can offload time-critical queries from the CPU. In this work, we describe the architecture of a 1U server that uses an AMD CPU to implement a full REDIS database coupled with three Xilinx ALVEO FPGA cards that offload 450M GET or SET Input/Output operations per second (IOPs).
The 1U rack-mount server has 170 Gigabits/Second, of network bandwidth implemented using five QSFP+ Ethernet ports. Two of the ports are used to interface with REDIS on the host CPU, while the other three QSFP+ ports handle queries directly in FPGA logic. The Hiredis C client was modified so that queries for small, fast-moving values are sent to the FPGA instead of the CPU. Queries serviced by the FPGA card respond with a network latency of under 500 nanoseconds.
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